Application Notes

Analog / Mixed-Signal / RF

• 1-027 - SmartSpice: Built-in Interconnect RC Network Reduction
• 1-026 - UTMOST-IV Delivers Full Capability of RPI TFT Models
• 1-025 - Managing Circuit Simulation Using VWF
• 1-024 - Introduction to VA-Debugger
• 1-023 - New Syntax for running VerilogA Models in Gateway/SmartSpice
• 1-022 - SmartSpice Circuit Design Using Local and Global Optimization
• 1-021 - Get the Best Performance From Your Verilog-A Model
• 1-020 - Debugging Verilog-A Flow Under Windows
• 1-019 - EDIF 200 - Conversion Guidelines for Importing Legacy EDIF Files for First-time Users
• 1-018 - HiSIM_HV Single Geometry Parameter Extraction with Automated UTMOST-IV Optimization
• 1-017 - Interactive Measurement in SmartView
• 1-016 - HiSIM_HV Local Optimization Templates Prepared for UTMOST III
• 1-015 - Performing Operation Point Analyses with Variable Sweeps
• 1-013 - Creating Netlists for Harmony Mixed-Signal Simulations
• 1-012 - Importing Standard design Libraries using EDIF 200
• 1-011 - Know More About Verilog-A Parser in SmartSpice
• 1-010 - Simulating Circuits with Parasitics and RCL Reduction
• 1-009 - Phase Noise Simulation with SmartSpiceRF
• 1-008 - Schematic Driven Process Corners Analysis
• 1-007 - Spiral Inductors PDK Flow Using QUEST, UTMOST IV, SmartSpice and SPAYN
• 1-006 - Guide To UTMOST IV Optimizers
• 1-005 - Transceiver Block Simulation with SmartSpiceRF
• 1-004 - Using Verilog-A to Simplify a Netlist
• 1-003 - SmartSpice SEU Module
• 1-002 - Physical 3D Single Event Upset Simulation of a SRAM Cell with Victory and SmartSpice SEE
• 1-001 - Salvaging Old Designs Through EDIF 200