 |
 |
 |
 |
Brochure
TFT
2D Amorphous and Polycrystalline Device Simulator
TFT is an advanced device technology simulator equipped with the physical models and specialized numerical techniques required to simulate amorphous or polysilicon devices including thin film transistors. Specialized applications include the large area display electronics such as Flat Panel Displays (FPDs) and solar cells.
TFT models the electrical effects of the distribution of defect states in the band gap of non-crystalline materials. Users can specify the Density Of States (DOS) as a function of energy for amorphous silicon and polysilicon for grain and grain boundaries as well as the capture cross-sections/lifetimes for electrons and holes. Models for mobility, impact ionization and band-to band tunneling can be modified by users to accurately predict device performance.
Key Features
- Energy dependent DOS
- Trap-to-Band phonon-assisted tunneling
- Band-to-Band tunneling effects
- Poole-Frenkel barrier lowering
- DIGBL (Drain Induced Grain barrier Lowering)
- DC, AC and transient simulation
Active Matrix Display Drivers
TFT can simulate active matrix display drivers used in large area flat-panel displays. This technology is based on low temperature processed a-Si:H or polysilicon TFTs. Electrical characterization of non-planar or multi-gate TFT structures is possible.
 |
 |
| A top gate n-channel Poly-Si TFT. This type of device is used for driving active matrix display elements. Contours of the potential at 0V are displayed. The Grain size is 600nm, Poly-Si thickness is 50nm and Gate oxide thickness is 140nm. | The distribution of defects is energy dependent. This plot illustrates the total donor and acceptor trap density levels including tail and gaussian distributions. Users can easily modify these DOS definitions to specify material characterizations using the C-Interpreter. |
 |
 |
| ATLAS models the reverse leakage at negative gate biases resulting from band-to-band tunneling and trap-assisted tunneling. Shown is a plot of the high reverse leakage for two different drain biases. | IV characteristics for a p and n channel poly-Si TFT. |
Simulation of a TFT Driven Pixel
TFT can be used with MixedMode to accurately simulate a pixel of a TFT LCD panel. As a more physically based alternative to compact TFT models, this allows designers to analyze and optimize LCD panel circuit designs and to evaluate the effects of parasitic components within each pixel. TFT handles multiple pixels to allow large scale simulation of the LCD panel.
 |
 |
| Shown is an equivalent circuit of a TFT pixel. MixedMode is used to simulate the electrical characteristics of the TFT driven pixel. | Effect of bit line programming of a TFT pixel. Drain voltage follows source voltage with a delay resulting from the external resistive and capacitative elements. |
Capacitance as AC Analysis
TFT can be used with small-signal AC analysis to extract figures-of-merit as well as capacitance information.
At higher drain voltages, Cgd increases slightly
which is different from bulk MOS devices. This phenomenon is more evident
in smaller devices where the Cgs decreases and Cgd increases with increasing
drain voltage, which can be explained by the kink effect of poly-Si
TFTs.
Grain Boundaries
Grain boundaries severely effect the mobility in TFTs. TFT
allows grain boundaries to be assigned within the channel as different regions.
These regions can then be assigned properties which differ from the properties
of the grain regions. These material properties can be supplied from a C-Inpterpreter
file or by using functions with TFT.
DIGBL Effect
This figure shows that the DIGBL effect from the on-state resistance at drain is 5V. The line of each gate voltage does not cross at one point. This is a unique phenomena of poly-Si TFTs.
IdVd characteristics as a function of gate bias.
When the drain bias is low, there is a high grain potential barrier.
As the drain bias is increased, the grain barrier bias is lowered and
so the drain current is increased. This is the DIGBL effect.
Solar Cells
TFT can be used with Luminous to simulate thin film solar cells made from amorphous silicon. Spectral, DC and transient responses can be extracted.
 |
 |
| A simple texture Si solar cell is shown. Photo-generation rates in the device are shown with periodic boundary conditions. The photogeneration rate is also shown. | A simple thin film amorphous Si solar cell is shown. This device has an opaque metal contact in the center of the structure. Photogeneration rates in the device are shown. Terminal currents can be evaluated to determine quantum efficiency of the cell. |
 |
 |
| Current voltage characteristics of a-Si solar cell under AM0 illumination. ISC is Short Circuit Current and VOC is Open Circuit Voltage. The Im and Vm is from the maximum power rectangle. | Current voltage characteristics of a-Si solar cell as a function of illumination power. |
Rev. 012908_03