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EliteADVANCED PHYSICAL ETCHING AND DEPOSITION SIMULATORElite is an advanced 2D topography simulator for modeling physical etching, deposition, reflow and CMP planarization processes for modern semiconductor technologies. Within the ATHENA framework, Elite provides seamless bi-directional integration with SSuprem4 and Optolith process simulators and contains an additional MC Deposit/Etch Simulator, which provides several Monte Carlo based atomistic etching and deposition models.
Advanced Semiconductor Topology Simulation Solutions
Models and Features
Deposition Models
Etch Models
Reflow Effects
Multi-Level Interconnect
Accurate descriptions of multi-level interconnect structures can be simulated with Elite. The figure shown above illustrates the capability to evaluate the tightly spaced interconnect lines and dielectric film uniformity of complicated interconnect structures. The interface with SSuprem4 allows doping and oxidation profiles to be included in the structure.
Microloading Effect
The etch models in Elite take into account both geometrical and advanced physical effects. The figure above shows the effect of microloading for Reactive Ion Etching. The effective etch rate on the bottom of the trench is smaller for narrower mask windows because the local ion flux is reduced due to shadowing effect.
Bonded SOI Wafer and Deep Trench Isolation Process
This example shows the combination of an Elite and SSuprem4 simulation of the deep trench isolation process on the Bonded SOI wafer. A bipolar power device has been formed in this structure. The reflow effect on the surface contact for the power automotive device is also considered.
Inter-metal Dielectric Void Formation
Elite can optimize a process to avoid formation of superfluous voids during deposition. The example above shows the use of two conductors (poly and aluminum) that are close together. The narrow gap between them can form a void after TEOS deposition as demonstrated in this example. The type of inter-metal dielectric material, thickness of this dielectric, method of insulation as well as design rules may affect the integrity of multi-level metallization.
Chemical Mechanical Polishing
Elite includes a module for evaluating the effects of CMP processes. The figure above illustrates the resulting surface evolution during a CMP of a dielectric test-structure. Such simulations could be used to investigate effects related to pattern density.
Metal Step Coverage After Reflow
This figure illustrates the ability of Elite to model metal step coverage in a contact via after reflow. Topographical descriptions such as this are useful for analyzing and avoiding failure mechanisms during multi-level deposits and patterning steps.
Deep Trench Etching and Epitaxial Growth
The combination of SSuprem4 and Elite can be used to optimize a Super Junction formation process, which is very popular in power device electronics. One of the methods of manufacturing of pillar-like p-n junctions consists of etching several deep trenches in n-type substrate with subsequent deposition/anneal or epitaxial growth of p-type silicon. This figure shows ELITE simulation of the Deep Trench Etching using RIE and CVD deposition of p-type material. Ssuprem4 is used to simulate the non-planar epitaxial growth with impurity redistribution and p-n junction formation.
Stress Dependent Etch Rate Model
Elite allows an estimation of the effect of heavy doping or stress on the etching rates. This figure demonstrates effect of the stress formed during mask pattering on the subsequent RIE etching.
Rev. 122107_07 |
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