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Brochure 1 Mb
SILOS is an easy-to-use IEEE-1364-2001 compliant Verilog simulator used by leading IC designers. An industry standard since 1986, its powerful interactive debugging features provide today’s most productive design environment for FPGA, PLD, ASIC and custom digital designs. SILOS can be used as a replacement for Synopsys VCS, Mentor Graphics ModelSim, Mentor Graphics Questa, Cadence Verilog-XL, Cadence Incisive Enterprise, Aldec Active-HDL/Riviera, Xilinx ISE, Altera Quartus II, Dolphin Integration SMASH, and provides the following key features:
- IEEE 1364 - 2001 Compliant Verilog multi-level HDL simulator at switch, gate, and behavioral levels with Programming Language Interface (PLI) support and save and restore capabilities. Supports RTCA/DO-254 validation methods.
- Hierarchy Explorer with “drag & drop” Interactive debugging with breakpoints of variables and expressions including code coverage without compile times and provides real-time viewing and error detection of all expressions, variables, modules, signals, vectors, and registers.
- Checks race, clock domain synchronization, fan-in and other hazardous timing conditions.
- Powerful built-in lint checker for syntax, semantic and design rule checking of synthesizability, Design-For-Testability (DFT), inferred registers, latches, state-machines and other sequential elements, also allows for Finite State Machines (FSM) analysis of redundant or unreachable states and un-testable circuits
Synopsys VCS, Mentor Graphics ModelSim, Mentor Graphics Questa, Cadence Verilog-XL, Cadence Incisive Enterprise, Aldec Active-HDL/Riviera, Xilinx ISE, Altera Quartus II, Dolphin Integration SMASH are the trademarks of their respective owners.