Guardian

3 Year Development Roadmap

Guardian DRC

• Enable DRC only on visible/active layers

Guardian LVS

• Device reduction effective property computation using LISA procedures
• Parallel/series merge and reduction of devices with consideration of specified parameter threshold
• Processing of primitive subcircuits
• Consider split gate ratio property in split gate structures
• Ignore specified nodes during LVS comparison process
• Creation of logic gates based upon tolerances of transistor parameters
• Flattening of internal hierarchy for given HCells during HLVS comparison
• Interpretation of subcircuits as distinct when names are the same but numbers of pins are different
• Reestablish hierarchical structure of netlists on base of logic gate recognition

Guardian NET

• Support layer prioritization functionality in connect statements
• Ability to rename specified layout cells
• Black boxing in hierarchical netlist extraction
• Enhance netlist extraction when connectivity problem with power or ground nets is detected
• Layout text ignore capability to disregard text labels in layout for specified cells
• Expand functionality for calculation of MOS device well proximity and advanced STI stress effect parameters used in 90 nm and below technologies
• Improve processing of hierarchical violations

Last Revised 05/11/2012