SmartSpice

90 Day Development Roadmap

SmartSpice Core

• Shared object algorithm for .ALTER functionality
• Integrate Rubberband with Verilog-A
• Develop linear RCL reduction based on system matrix size transformation
• Improve TMI/TMI2 integration using SmartSpice CMA model format
• Improve robustness of MonteCarlo multi-process distributed simulation algorithm using restarting approach
• Improve SmartSpice to Verilog-A structural API
• Random jitter analysis for P element
• Passivity checker for S element
• Delay handler for S element
• Improve accuracy of S element based on convolution algorithm
• Passivity, causality enforcement for S element
• Improve accuracy and performance of E element LAPLACE transform function
• Implement .OPTION EXPMAX

Solver

• Integrate SmartSpice with a family of iterative solvers

Models

• Develop compact SPICE model for a-IGZO TFTs
• Implement a technique for the implicit elimination of series resistances (selected by the HSIMSPEED=3 option) and an improved BYPASS option in the BSIMSOI4 model
• Implement the binning capability for BSIM-IMG model
• Improve the description of the transition between linear and saturation regions in the Universal Organic Thin-Film Transistor (UOTFT) model
• Add MULTITHREAD, VZERO, DCCAP, EXPERT options to HiSIM_HV2.0.0 model

Verilog-A

• Support hierarchical structures
• Support 'paramset' and 'localparam' statements
• Expand ddt() statement with second argument
• Support direct loading of pre-compiled Verilog-A files

HSPICE Compatibility

• Increase number of output functions for n-dimensional .NET analysis
• Develop .model card algorithm for Verilog-A
• Implement Monte Carlo, sweep, alter distributed simulation algorithm

SPECTRE Compatibility

• Develop Monte Carlo, Pole-zero, Fourier compatible analyses
• Develop SPECTRE-style output for circuit inventory, progress information, and statistics
• Support RAWPTS option for PSF ASCII output file format

FineSim compatibility

• Integrate block iterative solver for large circuit designs
• Develop runtime postprocessor functions:
  • CHKANODE
  • CHKDCPATH
  • CHKDEVOP
  • CHKRFTIME
  • CHKTIMING
  • CHKTOGGLE
  • CHKZNODE
  • CONNECT
• Develop “MOSFET Model Reuse Technique”

SmartView

Core

• Display simulation statistical information:
  • Total number of vectors
  • Number of each kind of vectors (i, v)
  • Number of points per vector

Last revised 3/6/2012