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Harmony:

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Product Family:

SmartSpice
Circuit Simulator

SILOS
Verilog Simulator

Verilog-A
Language for SmartSpice

Harmony

Analog/Mixed-Signal Simulator

Harmony is a single-kernel analog/mixed-signal circuit simulator that dynamically links in the capabilities of the SmartSpice Circuit Simulator and the SILOS Verilog Simulator at run time. Harmony combines accuracy, performance, capacity and flexibility to simulate circuits expressed in Verilog, SPICE, Verilog-A and Verilog-AMS.

Key Features

• Single-kernel engine provides unified mixed-signal initialization, synchronization, convergence, and accuracy
• Single window viewing and plotting for both analog and digital waveforms
• Support for Accellera 2.2 standard for Verilog-AMS and Verilog-A, IEEE 1364-2001 standard for Verilog-HDL and Programming Language Interface (PLI), and HSPICE™ netlist/command
• Provides the most accurate circuit simulation results and robust convergence for critical mixed-signal designs
• Silvaco's strong encryption is available to protect valuable customer and third party intellectual property.

Single Kernel Architecture

• Eliminate iterations between analog-only and digital-only simulations and the risk of releasing a design without verifying composite analog and digital circuit behavior
• Single kernel simulator dynamically links in the capabilities of the SmartSpice Circuit Simulator and the SILOS Verilog Simulator
• Harmony language synchronization uses Accellera 2.2 Verilog-AMS standard connect modules for all analog to digital interfaces
• Harmony includes default connection modules that meet designer’s expectations for accuracy, flexibility of use, and speed
• Harmony automatically provides timing sychronization between analog and digital parts of circuits
• Integrated waveform viewer displays analog and digital waveforms on same scale
  

Harmony Analog/Mixed-Signal Simulator with Integrated AMS Viewer

Single Parser Support Verilog and SPICE

• Harmony parser partitions analog or digital blocks to the different simulation engines as per the current Accellera Verilog-AMS standards
• Supports SPICE netlists, options, analysis, stimulus and response in Berkeley or HSPICE® format
• Verilog-A language supports top-down design via behavioral modeling and bottom-up verification
• Verilog-A language enables compact model engineers to easily develop proprietary models for specific semiconductor technology behavior (leakage, weak/subthreshold operation, etc.)
• Supports Verilog-HDL with IEEE-1364-2001 compliant Verilog simulator with standard Programming Language Interface (PLI)
• Timing back-annotation supported through SDF

Single Viewer for Analog and Digital

• Easy-to-use graphic user interface provides productive environment for novices and experts—selected by 7 major Verilog textbooks
• Comprehensive Project Manager saves preferences, settings, directories, and options in a file for efficient multi-project setup
• Multi-window customizable Data Analyzer controls pan and zoom, timing markers, using interactive “drag & drop” capture, and display for signals and expressions for analog and digital waveforms
• Harmony Interactive Environment enables real-time access and analysis of all expressions, variables, modules, signals, vectors, and registers
• Consistent interactive methods for signal selection, setting time-scale, bus radix, status window, timing marker, bookmark, and bus definition
• SmartView offers complete post-processing tools for composite diagrams, histograms, vector calculator, FFT analysis, and eye diagram plots

Data Tips in the Source Window display value, scope, and time of the highlighted expression at the T1 marker in the Data Analyzer	Harmony can save vectors within any hierarchical subcircuit for SmartView graphical analysis including annotated eye diagram, constellation, FFT analysis, and vector calculator

Interactive Debugging Environment

• Interactive, interpreted Verilog-AMS environment provides a set of multi-tasking utilities to edit HDL source, set incremental breakpoints, stepping or timed simulation, real-time viewing, and error detection
• Multi-window customizable Data Analyzer controls pan and zoom, timing markers, using interactive “drag & drop” capture, and display for signals and expressions for analog and digital waveforms
• Trace Mode graphically traces all fan-in connections to any signal through all levels of circuit hierarchy instantly
• Watch window displays or forces state values of specified signals and variables while single-stepping—all set up through “drag & drop” for designer convenience
• Interactive Source Code Editor displays line numbers for stop, start, and breakpoints, Data Tips to view the values of analog and digital variables and expressions, and Verilog code coverage information
  

Accuracy, Convergence and Performance

• 100% HSPICE™ compatible for netlists, models, analysis features, and results
• Provides the most accurate circuit simulation results for critical analog designs
• Offers largest capacity of any true SPICE circuit simulator – up to 400,000 active devices in 32-bit and 8 million active devices in 64-bit version
• Fastest run-time of any true SPICE circuit simulator and the only SPICE supporting multiple threads for parallel operation
• Multiple solvers and stepping algorithms for robust convergence
• Largest collection of calibrated SPICE models for traditional technologies (Bipolar, CMOS) and emerging technologies (e.g., TFT, SOI, HBT, SiGe)
• Convergence of the analog netlist in the mixed-signal circuit is dependent on multiple solvers and stepping algorithms available to the analog simulator in the mixed-signal environment

Rev. 101410_17