Verilog Simulation Software Development Engineer

Santa Clara, CA

Design, develop and maintain Silvaco's long established SILOS Verilog simulation software. A number of positions are open in the area of Verilog and VHDL compilers and interpreters.

Must have:

• MSEE/MSCS degree or higher
• Proficiency in C++ on Linux or Windows
• Parser development experience
• Familiarity with LEX/YACC or similar lexical and syntax parsers
• At least 5 years hands-on experience with some aspect of Verilog or VHDL software development

Other preferred skills:

• Familiarity with Verilog-A, Verilog-AMS, VHDL-AMS languages
• Familiarity with circuit simulation

Please quote ref. SW-VLG-CA when applying

By Email: jobs@silvaco.com